System with cache-coherent memory and server-linking switch

ABSTRACT

A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of U.S. patent application Ser. No.17/026,074, filed Sep. 18, 2020, which claims priority to and thebenefit of U.S. Provisional Application No. 63/031,508, filed May 28,2020, entitled “EXTENDING MEMORY ACCESSES WITH NOVEL CACHE COHERENCECONNECTS”, and priority to and the benefit of U.S. ProvisionalApplication No. 63/031,509, filed May 28, 2020, entitled “POOLING SERVERMEMORY RESOURCES FOR COMPUTE EFFICIENCY”, and priority to and thebenefit of U.S. Provisional Application No. 63/068,054, filed Aug. 20,2020, entitled “SYSTEM WITH CACHE-COHERENT MEMORY AND SERVER-LINKINGSWITCH FIELD”, and priority to and the benefit of U.S. ProvisionalApplication No. 63/057,746, filed Jul. 28, 2020, entitled “DISAGGREGATEDMEMORY ARCHITECTURE WITH NOVEL INTERCONNECTS”, and priority to and thebenefit of U.S. Provisional Application No. 63/006,073, filed Apr. 6,2020, entitled “SYSTEMS, METHODS, AND APPARATUSES FOR MEMORY ACCESSUSING CACHE COHERENT INTERCONNECTS”, the entire contents of all whichare incorporated herein by reference.

FIELD

One or more aspects of embodiments according to the present disclosurerelate to computing systems, and more particularly to a system andmethod for managing memory resources in a system including one or moreservers.

BACKGROUND

The present background section is intended to provide context only, andthe disclosure of any embodiment or concept in this section does notconstitute an admission that said embodiment or concept is prior art.

Some server systems may include collections of servers connected by anetwork protocol. Each of the servers in such a system may includeprocessing resources (e.g., processors) and memory resources (e.g.,system memory). It may be advantageous, in some circumstances, for aprocessing resource of one server to access a memory resource of anotherserver, and it may be advantageous for this access to occur whileminimizing the processing resources of either server.

Thus, there is a need for an improved system and method for managingmemory resources in a system including one or more servers.

SUMMARY

In some embodiments, a data storage and processing system includes aplurality of servers connected by a server-linking switch. Each servermay include one or more processing circuits, system memory, and one ormore memory modules connected to the processing circuits through acache-coherent switch. The cache coherent switch may be connected to theserver-linking switch and it may include a controller (e.g., afield-programmable gate array (FPGA) or an application specificintegrated circuit (ASIC)) providing it with enhanced capabilities.These capabilities may include virtualizing the memory modules, enablingthe switch to store data in memory modules using an underlyingtechnology well suited to the storage requirements (e.g., latency,bandwidth, or persistence) of the data being stored. The cache-coherentswitch may receive the storage requirements as a result of theserequirements having been transmitted to it by the processing circuits,or as a result of monitoring access patterns. The enhanced capabilitiesmay further include enabling the server to interact with memory ofanother server without having to access a processor such as a centralprocessing unit (CPU) (e.g., by performing remote direct memory access(RDMA)).

According to an embodiment of the present invention, there is provided asystem, including: a first server, including: a stored-programprocessing circuit, a cache-coherent switch, and a first memory module;and a second server; and a server-linking switch connected to the firstserver and to the second server, wherein: the first memory module isconnected to the cache-coherent switch, the cache-coherent switch isconnected to the server-linking switch, and the stored-programprocessing circuit is connected to the cache-coherent switch.

In some embodiments, the server-linking switch includes a PeripheralComponent Interconnect Express (PCIe) switch.

In some embodiments, the server-linking switch includes a ComputeExpress Link (CXL) switch.

In some embodiments, the server-linking switch includes a top of rack(ToR) CXL switch.

In some embodiments, the server-linking switch is configured to discoverthe first server.

In some embodiments, the server-linking switch is configured to causethe first server to reboot.

In some embodiments, the server-linking switch is configured to causethe cache-coherent switch to disable the first memory module.

In some embodiments, the server-linking switch is configured to transmitdata from the second server to the first server, and to perform flowcontrol on the data.

In some embodiments, the system further includes a third serverconnected to the server-linking switch, wherein: the server-linkingswitch is configured to: receive a first packet, from the second server,receive a second packet, from the third server, and transmit the firstpacket and the second packet to the first server.

In some embodiments, the system further includes a second memory moduleconnected to the cache-coherent switch, wherein the first memory moduleincludes volatile memory and the second memory module includespersistent memory.

In some embodiments, the cache-coherent switch is configured tovirtualize the first memory module and the second memory module.

In some embodiments, the first memory module includes flash memory, andthe cache-coherent switch is configured to provide a flash translationlayer for the flash memory.

In some embodiments, the first server includes an expansion socketadapter, connected to an expansion socket of the first server, theexpansion socket adapter including: the cache-coherent switch; and amemory module socket, the first memory module being connected to thecache-coherent switch through the memory module socket.

In some embodiments, the memory module socket includes an M.2 socket.

In some embodiments: the cache-coherent switch is connected to theserver-linking switch through a connector, and the connector is on theexpansion socket adapter.

According to an embodiment of the present invention, there is provided amethod for performing remote direct memory access in a computing system,the computing system including: a first server, a second server, a thirdserver, and a server-linking switch connected to the first server, tothe second server, and to the third server, the first server including:a stored-program processing circuit, a cache-coherent switch, and afirst memory module, the method including: receiving, by theserver-linking switch, a first packet, from the second server,receiving, by the server-linking switch, a second packet, from the thirdserver, and transmitting the first packet and the second packet to thefirst server.

In some embodiments, the method further includes: receiving, by thecache-coherent switch, a remote direct memory access (RDMA) request, andsending, by the cache-coherent switch, a RDMA response.

In some embodiments, the receiving of the RDMA request includesreceiving the RDMA request through the server-linking switch.

In some embodiments, the method further includes: receiving, by thecache-coherent switch, a read command, from the stored-programprocessing circuit, for a first memory address, translating, by thecache-coherent switch, the first memory address to a second memoryaddress, and retrieving, by the cache-coherent switch, data from thefirst memory module at the second memory address.

According to an embodiment of the present invention, there is provided asystem, including: a first server, including: a stored-programprocessing circuit, cache-coherent switching means, a first memorymodule; and a second server; and a server-linking switch connected tothe first server and to the second server, wherein: the first memorymodule is connected to the cache-coherent switching means, thecache-coherent switching means is connected to the server-linkingswitch, and the stored-program processing circuit is connected to thecache-coherent switching means.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings provided herein are for purpose of illustrating certainembodiments only; other embodiments, which may not be explicitlyillustrated, are not excluded from the scope of this disclosure.

These and other features and advantages of the present disclosure willbe appreciated and understood with reference to the specification,claims, and appended drawings wherein:

FIG. 1A is a block diagram of a system for attaching memory resources tocomputing resources using a cache-coherent connection, according to anembodiment of the present disclosure;

FIG. 1B is a block diagram of a system, employing expansion socketadapters, for attaching memory resources to computing resources using acache-coherent connection, according to an embodiment of the presentdisclosure;

FIG. 1C is a block diagram of a system for aggregating memory employingan Ethernet ToR switch, according to an embodiment of the presentdisclosure;

FIG. 1D is a block diagram of a system for aggregating memory employingan Ethernet ToR switch and an expansion socket adapter, according to anembodiment of the present disclosure;

FIG. 1E is a block diagram of a system for aggregating memory, accordingto an embodiment of the present disclosure;

FIG. 1F is a block diagram of a system for aggregating memory, employingan expansion socket adapter, according to an embodiment of the presentdisclosure;

FIG. 1G is a block diagram of a system for disaggregating servers,according to an embodiment of the present disclosure;

FIG. 2A is a flow chart for an example method of performing a remotedirect memory access (RDMA) transfer, bypassing processing circuits, forembodiments illustrated in FIGS. 1A-1G, according to an embodiment ofthe present disclosure;

FIG. 2B is a flow chart for an example method of performing an RDMAtransfer, with the participation of processing circuits, for embodimentsillustrated in FIGS. 1A-1D, according to an embodiment of the presentdisclosure;

FIG. 2C is a flow chart for an example method of performing an RDMAtransfer, through a Compute Express Link (CXL) switch, for embodimentsillustrated in FIGS. 1E and 1F, according to an embodiment of thepresent disclosure; and

FIG. 2D is a flow chart for an example method of performing an RDMAtransfer, through a CXL switch for the embodiment illustrated in FIG.1G, according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appendeddrawings is intended as a description of exemplary embodiments of asystem and method for managing memory resources provided in accordancewith the present disclosure and is not intended to represent the onlyforms in which the present disclosure may be constructed or utilized.The description sets forth the features of the present disclosure inconnection with the illustrated embodiments. It is to be understood,however, that the same or equivalent functions and structures may beaccomplished by different embodiments that are also intended to beencompassed within the scope of the disclosure. As denoted elsewhereherein, like element numbers are intended to indicate like elements orfeatures.

Peripheral Component Interconnect Express (PCIe) can refer to a computerinterface which may have a relatively high and variable latency that canlimit its usefulness in making connections to memory. CXL is an openindustry standard for communications over PCIe 5.0, which can providefixed, relatively short packet sizes, and, as a result, may be able toprovide relatively high bandwidth and relatively low, fixed latency. Assuch, CXL may be capable of supporting cache coherence and CXL may bewell suited for making connections to memory. CXL may further be used toprovide connectivity between a host and accelerators, memory devices,and network interface circuits (or “network interface controllers” ornetwork interface cards” (NICs)) in a server.

Cache coherent protocols such as CXL may also be employed forheterogeneous processing, e.g., in scalar, vector, and buffered memorysystems. CXL may be used to leverage the channel, the retimers, the PHYlayer of a system, the logical aspects of the interface, and theprotocols from PCIe 5.0 to provide a cache-coherent interface. The CXLtransaction layer may include three multiplexed sub-protocols that runsimultaneously on a single link and can be referred to as CXL.io,CXL.cache, and CXL.memory. CXL.io may include I/O semantics, which maybe similar to PCIe. CXL.cache may include caching semantics, andCXL.memory may include memory semantics; both the caching semantics andthe memory semantics may be optional. Like PCIe, CXL may support (i)native widths of ×16, ×8, and ×4, which may be partitionable, (ii) adata rate of 32 GT/s, degradable to 8 GT/s and 16 GT/s, 128b/130b, (iii)300 W (75 W in a ×16 connector), and (iv) plug and play. To support plugand play, either a PCIe or a CXL device link may start training in PCIein Gen1, negotiate CXL, complete Gen 1-5 training and then start CXLtransactions.

In some embodiments, the use of CXL connections to an aggregation, or“pool”, of memory (e.g., a quantity of memory, including a plurality ofmemory cells connected together) may provide various advantages, in asystem that includes a plurality of servers connected together by anetwork, as discussed in further detail below. For example, a CXL switchhaving further capabilities in addition to providing packet-switchingfunctionality for CXL packets (referred to herein as an “enhancedcapability CXL switch”) may be used to connect the aggregation of memoryto one or more central processing units (CPUs) (or “central processingcircuits”) and to one or more network interface circuits (which may haveenhanced capability). Such a configuration may make it possible (i) forthe aggregation of memory to include various types of memory, havingdifferent characteristics, (ii) for the enhanced capability CXL switchto virtualize the aggregation of memory, and to store data of differentcharacteristics (e.g., frequency of access) in appropriate types ofmemory, (iii) for the enhanced capability CXL switch to support remotedirect memory access (RDMA) so that RDMA may be performed with little orno involvement from the server's processing circuits. As used herein, to“virtualize” memory means to perform memory address translation betweenthe processing circuit and the memory.

A CXL switch may (i) support memory and accelerator dis-aggregationthrough single level switching, (ii) enable resources to be off-linedand on-lined between domains, which may enable time-multiplexing acrossdomains, based on demand, and (iii) support virtualization of downstreamports. CXL may be employed to implement aggregated memory, which mayenable one-to-many and many-to-one switching (e.g., it may be capable of(i) connecting multiple root ports to one end point, (ii) connecting oneroot port to multiple end points, or (iii) connecting multiple rootports to multiple end points), with aggregated devices being, in someembodiments, partitioned into multiple logical devices each with arespective LD-ID (logical device identifier). In such an embodiment aphysical device may be partitioned into a plurality of logical devices,each visible to a respective initiator. A device may have one physicalfunction (PF) and a plurality (e.g., 16) isolated logical devices. Insome embodiments the number of logical devices (e.g., the number ofpartitions) may be limited (e.g. to 16), and one control partition(which may be a physical function used for controlling the device) mayalso be present.

In some embodiments, a fabric manager may be employed to (i) performdevice discovery and virtual CXL software creation, and to (ii) bindvirtual ports to physical ports. Such a fabric manager may operatethrough connections over an SMBus sideband. The fabric manager may beimplemented in hardware, or software, or firmware, or in a combinationthereof, and it may reside, for example, in the host, in one of thememory modules 135, or in the enhanced capability CXL switch 130, orelsewhere in the network. The fabric manager may issue commandsincluding commands issued through a sideband bus or through the PCIetree.

Referring to FIG. 1A, in some embodiments, a server system includes aplurality of servers 105, connected together by a top of rack (ToR)Ethernet switch 110. While this switch is described as using Ethernetprotocol, any other suitable network protocol may be used. Each serverincludes one or more processing circuits 115, each connected to (i)system memory 120 (e.g., Double Data Rate (version 4) (DDR4) memory orany other suitable memory), (ii) one or more network interface circuits125, and (iii) one or more CXL memory modules 135. Each of theprocessing circuits 115 may be a stored-program processing circuit,e.g., a central processing unit (CPU (e.g., an x86 CPU), a graphicsprocessing unit (GPU), or an ARM processor. In some embodiments anetwork interface circuit 125 may be embedded in (e.g., on the samesemiconductor chip as, or in the same module as) one of the memorymodules 135, or a network interface circuit 125 may be separatelypackaged from the memory modules 135.

As used herein, a “memory module” is a package (e.g., a packageincluding a printed circuit board and components connected to it, or anenclosure including a printed circuit board) including one or morememory dies, each memory die including a plurality of memory cells. Eachmemory die, or each of a set of groups of memory dies, may be in apackage (e.g., an epoxy mold compound (EMC) package) soldered to theprinted circuit board of the memory module (or connected to the printedcircuit board of the memory module through a connector). Each of thememory modules 135 may have a CXL interface and may include a controller137 (e.g., an FPGA, an ASIC, a processor, and/or the like) fortranslating between CXL packets and the memory interface of the memorydies, e.g., the signals suitable for the memory technology of the memoryin the memory module 135. As used herein, the “memory interface” of thememory dies is the interface that is native to the technology of thememory dies, e.g., in the case of DRAM e.g., the memory interface may beword lines and bit lines. A memory module may also include a controller137 which may provide enhanced capabilities, as described in furtherdetail below. The controller 137 of each memory modules 135 may beconnected to a processing circuit 115 through a cache-coherentinterface, e.g., through the CXL interface. The controller 137 may alsofacilitate data transmissions (e.g., RDMA requests) between differentservers 105, bypassing the processing circuits 115. The ToR Ethernetswitch 110 and the network interface circuits 125 may include an RDMAinterface to facilitate RDMA requests between CXL memory devices ondifferent servers (e.g., the ToR Ethernet switch 110 and the networkinterface circuits 125 may provide hardware offload or hardwareacceleration of RDMA over Converged Ethernet (RoCE), Infiniband, andiWARP packets).

The CXL interconnects in the system may comply with a cache coherentprotocol such as the CXL 1.1 standard, or, in some embodiments, with theCXL 2.0 standard, with a future version of CXL, or any other suitableprotocol (e.g., cache coherent protocol). The memory modules 135 may bedirectly attached to the processing circuits 115 as shown, and the topof rack Ethernet switch 110 may be used for scaling the system to largersizes (e.g., with larger numbers of servers 105).

In some embodiments, each server can be populated with multipledirect-attached CXL attached memory modules 135, as shown in FIG. 1A.Each memory module 135 may expose a set of base address registers (BARs)to the host's Basic Input/Output System (BIOS) as a memory range. One ormore of the memory modules 135 may include firmware to transparentlymanage its memory space behind the host OS map. Each of the memorymodules 135 may include one of, or a combination of, memory technologiesincluding, for example (but not limited to) Dynamic Random Access Memory(DRAM), not-AND (NAND) flash, High Bandwidth Memory (HBM), and Low-PowerDouble Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM)technologies, and may also include a cache controller or separaterespective split controllers for different technology memory devices(for memory modules 135 that combine several memory devices of differenttechnologies). Each memory module 135 may include different interfacewidths (×4-×16), and may be constructed according to any of variouspertinent form factors, e.g., U.2, M.2, half height, half length (HHHL),full height, half length (FHHL), E1.S, E1.L, E3.S, and E3.H.

In some embodiments, as mentioned above, the enhanced capability CXLswitch 130 includes an FPGA (or ASIC) controller 137 and providesadditional features beyond switching of CXL packets. The controller 137of the enhanced capability CXL switch 130 may also act as a managementdevice for the memory modules 135 and help with host control planeprocessing, and it may enable rich control semantics and statistics. Thecontroller 137 may include an additional “backdoor” (e.g., 100 gigabitEthernet (GbE)) network interface circuit 125. In some embodiments, thecontroller 137 presents as a CXL Type 2 device to the processingcircuits 115, which enables the issuing of cache invalidate instructionsto the processing circuits 115 upon receiving remote write requests. Insome embodiments, DDIO technology is enabled, and remote data is firstpulled to last level cache (LLC) of the processing circuit and laterwritten to the memory modules 135 (from cache). As used herein, a “Type2” CXL Device is one that can initiate transactions and that implementsan optional coherent cache and host-managed device memory and for whichapplicable transaction types include all CXL.cache and all CXL.memtransactions.

As mentioned above, one or more of the memory modules 135 may includepersistent memory, or “persistent storage” (i.e., storage within whichdata is not lost when external power is disconnected). If a memorymodule 135 is presented as a persistent device, the controller 137 ofthe memory module 135 may manage the persistent domain, e.g., it maystore, in the persistent storage data identified (e.g., as a result ofan application making a call to a corresponding operating systemfunction) by a processing circuit 115 as requiring persistent storage.In such an embodiment, a software API may flush caches and data to thepersistent storage.

In some embodiments, direct memory transfer to the memory modules 135from the network interface circuits 125 is enabled. Such transfers maybe a one-way transfers to remote memory for fast communication in adistributed system. In such an embodiment, the memory modules 135 mayexpose hardware details to the network interface circuits 125 in thesystem to enable faster RDMA transfers. In such a system, two scenariosmay occur, depending on whether the Data Direct I/O (DDIO) of theprocessing circuit 115 is enabled or disabled. DDIO may enable directcommunication between an Ethernet controller or an Ethernet adapter anda cache of a processing circuit 115. If the DDIO of the processingcircuit 115 is enabled, the transfer's target may be the last levelcache of the processing circuit, from which the data may subsequently beautomatically flushed to the memory modules 135. If the DDIO of theprocessing circuit 115 is disabled, the memory modules 135 may operatein device-bias mode to force accesses to be directly received by thedestination memory module 135 (without DDIO). An RDMA-capable networkinterface circuit 125 with host channel adapter (HCA), buffers, andother processing, may be employed to enable such an RDMA transfer, whichmay bypass the target memory buffer transfer that may be present inother modes of RDMA transfer. For example, in such an embodiment, theuse of a bounce buffer (e.g., a buffer in the remote server, when theeventual destination in memory is in an address range not supported bythe RDMA protocol) may be avoided. In some embodiments, RDMA usesanother physical medium option, other than Ethernet (e.g., for use witha switch that is configured to handle other network protocols). Examplesof inter-server connections that may enable RDMA include (but are notlimited to) Infiniband, RDMA over Converged Ethernet (RoCE) (which usesEthernet User Datagram Protocol (UDP)), and iWARP (which usestransmission control protocol/Internet protocol (TCP/IP)).

FIG. 1B shows a system similar to that of FIG. 1A, in which theprocessing circuits 115 are connected to the network interface circuits125 through the memory modules 135. The memory modules 135 and thenetwork interface circuits 125 are on expansion socket adapters 140.Each expansion socket adapter 140 may plug into an expansion socket 145,e.g., a M.2 connector, on the motherboard of the server 105. As such,the server may be any suitable (e.g., industry standard) server,modified by the installation of the expansion socket adapters 140 inexpansion sockets 145. In such an embodiment, (i) each network interfacecircuit 125 may be integrated into a respective one of the memorymodules 135, or (ii) each network interface circuit 125 may have a PCIeinterface (the network interface circuit 125 may be a PCIe endpoint(i.e., a PCIe slave device)), so that the processing circuit 115 towhich it is connected (which may operate as the PCIe master device, or“root port”) may communicate with it through a root port to endpointPCIe connection, and the controller 137 of the memory module 135 maycommunicate with it through a peer-to-peer PCIe connection.

According to an embodiment of the present invention, there is provided asystem, including: a first server, including: a stored-programprocessing circuit, a first network interface circuit, and a firstmemory module, wherein: the first memory module includes: a first memorydie, and a controller, the controller being connected: to the firstmemory die through a memory interface, to the stored-program processingcircuit through a cache-coherent interface, and to the first networkinterface circuit. In some embodiments: the first memory module furtherincludes a second memory die, the first memory die includes volatilememory, and the second memory die includes persistent memory. In someembodiments, the persistent memory includes NAND flash. In someembodiments, the controller is configured to provide a flash translationlayer for the persistent memory. In some embodiments, the cache-coherentinterface includes a Compute Express Link (CXL) interface. In someembodiments, the first server includes an expansion socket adapter,connected to an expansion socket of the first server, the expansionsocket adapter including: the first memory module; and the first networkinterface circuit. In some embodiments, the controller of the firstmemory module is connected to the stored-program processing circuitthrough the expansion socket. In some embodiments, the expansion socketincludes an M.2 socket. In some embodiments, the controller of the firstmemory module is connected to the first network interface circuit by apeer to peer Peripheral Component Interconnect Express (PCIe)connection. In some embodiments, the system further includes: a secondserver, and a network switch connected to the first server and to thesecond server. In some embodiments, the network switch includes a top ofrack (ToR) Ethernet switch. In some embodiments, the controller of thefirst memory module is configured to receive straight remote directmemory access (RDMA) requests, and to send straight RDMA responses. Insome embodiments, the controller of the first memory module isconfigured to receive straight remote direct memory access (RDMA)requests through the network switch and through the first networkinterface circuit, and to send straight RDMA responses through thenetwork switch and through the first network interface circuit. In someembodiments, the controller of the first memory module is configured to:receive data, from the second server; store the data in the first memorymodule; and send, to the stored-program processing circuit, a commandfor invalidating a cache line. In some embodiments, the controller ofthe first memory module includes a field programmable gate array (FPGA)or an application-specific integrated circuit (ASIC). According to anembodiment of the present invention, there is provided a method forperforming remote direct memory access in a computing system, thecomputing system including: a first server and a second server, thefirst server including: a stored-program processing circuit, a networkinterface circuit, and a first memory module including a controller, themethod including: receiving, by the controller of the first memorymodule, a straight remote direct memory access (RDMA) request; andsending, by the controller of the first memory module, a straight RDMAresponse. In some embodiments: the computing system further includes anEthernet switch connected to the first server and to the second server,and the receiving of the straight RDMA request includes receiving thestraight RDMA request through the Ethernet switch. In some embodiments,the method further includes: receiving, by the controller of the firstmemory module, a read command, from the stored-program processingcircuit, for a first memory address, translating, by the controller ofthe first memory module, the first memory address to a second memoryaddress, and retrieving, by the controller of the first memory module,data from the first memory module at the second memory address. In someembodiments, the method further includes: receiving data, by thecontroller of the first memory module, storing, by the controller of thefirst memory module, the data in the first memory module, and sending,by the controller of the first memory module, to the stored-programprocessing circuit, a command for invalidating a cache line. Accordingto an embodiment of the present invention, there is provided a system,including: a first server, including: a stored-program processingcircuit, a first network interface circuit, and a first memory module,wherein: the first memory module includes: a first memory die, andcontroller means, the controller means being connected: to the firstmemory die through a memory interface, to the stored-program processingcircuit through a cache-coherent interface, and to the first networkinterface circuit.

Referring to FIG. 1C, in some embodiments, a server system includes aplurality of servers 105, connected together by a top of rack (ToR)Ethernet switch 110. Each server includes one or more processingcircuits 115, each connected to (i) system memory 120 (e.g., DDR4memory), (ii) one or more network interface circuits 125, and (iii) anenhanced capability CXL switch 130. The enhanced capability CXL switch130 may be connected to a plurality of memory modules 135. That is, thesystem of FIG. 1C includes a first server 105, including astored-program processing circuit 115, a network interface circuit 125,a cache-coherent switch 130, and a first memory module 135. In thesystem of FIG. 1C, the first memory module 135 is connected to thecache-coherent switch 130, the cache-coherent switch 130 is connected tothe network interface circuit 125, and the stored-program processingcircuit 115 is connected to the cache-coherent switch 130.

The memory modules 135 may be grouped by type, form factor, ortechnology type (e.g., DDR4, DRAM, LDPPR, high bandwidth memory (HBM),or NAND flash, or other persistent storage (e.g., solid state drivesincorporating NAND flash)). Each memory module may have a CXL interfaceand include an interface circuit for translating between CXL packets andsignals suitable for the memory in the memory module 135. In someembodiments, these interface circuits are instead in the enhancedcapability CXL switch 130, and each of the memory modules 135 has aninterface that is the native interface of the memory in the memorymodule 135. In some embodiments, the enhanced capability CXL switch 130is integrated into (e.g., in an M.2 form factor package with, orintegrated into a single integrated circuit with other components of) amemory module 135.

The ToR Ethernet switch 110 may include interface hardware to facilitateRDMA requests between aggregated memory devices on different servers.The enhanced capability CXL switch 130 may include one or more circuits(e.g., it may include an FPGA or an ASIC) to (i) route data to differentmemory types based on workload (ii) virtualize host addresses to deviceaddresses and/or (iii) facilitate RDMA requests between differentservers, bypassing the processing circuits 115.

The memory modules 135 may be in an expansion box (e.g., in the samerack as the enclosure housing the motherboard of the enclosure), whichmay include a predetermined number (e.g., more than 20 or more than 100)memory modules 135, each plugged into a suitable connector. The modulesmay be in an M.2 form factor, and the connectors may be M.2 connectors.In some embodiments, the connections between servers are over adifferent network, other than Ethernet, e.g., they may be wirelessconnections such as WiFi or 5G connections. Each processing circuit maybe an x86 processor or another processor, e.g., an ARM processor or aGPU. The PCIe links on which the CXL links are instantiated may be PCIe5.0 or another version (e.g., an earlier version or a later (e.g.,future) version (e.g., PCIe 6.0). In some embodiments, a differentcache-coherent protocol is used in the system instead of, or in additionto, CXL, and a different cache coherent switch may be used instead of,or in addition to, the enhanced capability CXL switch 130. Such a cachecoherent protocol may be another standard protocol or a cache coherentvariant of the standard protocol (in a manner analogous to the manner inwhich CXL is a variant of PCIe 5.0). Examples of standard protocolsinclude, but are not limited to, non-volatile dual in-line memory module(version P) (NVDIMM-P), Cache Coherent Interconnect for Accelerators(CCIX), and Open Coherent Accelerator Processor Interface (OpenCAPI).

The system memory 120 may include, e.g., DDR4 memory, DRAM, HBM, orLDPPR memory. The memory modules 135 may be partitioned or contain cachecontrollers to handle multiple memory types. The memory modules 135 maybe in different form factors, examples of which include but are notlimited to HHHL, FHHL, M.2, U.2, mezzanine card, daughter card, E1.S,E1.L, E3.L, and E3.S.

In some embodiments, the system implements a aggregated architecture,including multiple servers, with each server aggregated with multipleCXL-attached memory modules 135. Each of the memory modules 135 maycontain multiple partitions that can separately be exposed as memorydevices to multiple processing circuits 115. Each input port of theenhanced capability CXL switch 130 may independently access multipleoutput ports of the enhanced capability CXL switch 130 and the memorymodules 135 connected thereto. As used herein, an “input port” or“upstream port” of the enhanced capability CXL switch 130 is a portconnected to (or suitable for connecting to) a PCIe root port, and an“output port” or “downstream port” of the enhanced capability CXL switch130 is a port connected to (or suitable for connecting to) a PCIeendpoint. As in the case of the embodiment of FIG. 1A, each memorymodule 135 may expose a set of base address registers (BARs) to hostBIOS as a memory range. One or more of the memory modules 135 mayinclude firmware to transparently manage its memory space behind thehost OS map.

In some embodiments, as mentioned above, the enhanced capability CXLswitch 130 includes an FPGA (or ASIC) controller 137 and providesadditional features beyond switching of CXL packets. For example, it may(as mentioned above) virtualize the memory modules 135, i.e., operate asa translation layer, translating between processing circuit-sideaddresses (or “processor-side” addresses, i.e., addresses that areincluded in memory read and write commands issued by the processingcircuits 115) and memory-side addresses (i.e., addresses employed by theenhanced capability CXL switch 130 to address storage locations in thememory modules 135), thereby masking the physical addresses of thememory modules 135 and presenting a virtual aggregation of memory. Thecontroller 137 of the enhanced capability CXL switch 130 may also act asa management device for the memory modules 135 and facilitate with hostcontrol plane processing. The controller 137 may transparently move datawithout the participation of the processing circuits 115 and accordinglyupdate the memory map (or “address translation table”) so thatsubsequent accesses function as expected. The controller 137 may containa switch management device that (i) can bind and unbind the upstream anddownstream connections during runtime as appropriate, and (iii) canenable rich control semantics and statistics associated with datatransfers into and out of the memory modules 135. The controller 137 mayinclude an additional “backdoor” 100 GbE or other network interfacecircuit 125 (in addition to the network interface used to connect to thehost) for connecting to other servers 105 or to other networkedequipment. In some embodiments, the controller 137 presents as a Type 2device to the processing circuits 115, which enables the issuing ofcache invalidate instructions to the processing circuits 115 uponreceiving remote write requests. In some embodiments, DDIO technology isenabled, and remote data is first pulled to last level cache (LLC) ofthe processing circuit 115 and later written to the memory modules 135(from cache).

As mentioned above, one or more of the memory modules 135 may includepersistent storage. If a memory module 135 is presented as a persistentdevice, the controller 137 of the enhanced capability CXL switch 130 maymanage the persistent domain (e.g., it may store, in the persistentstorage, data identified (e.g., by the use of a corresponding operatingsystem function) by a processing circuit 115 as requiring persistentstorage. In such an embodiment, a software API may flush caches and datato the persistent storage.

In some embodiments, direct memory transfer to the memory modules 135may be performed in a manner analogous to that described above for theembodiment of FIGS. 1A and 1B, with operations performed by thecontrollers of the memory modules 135 being, performed by the controller137 of the enhanced capability CXL switch 130.

As mentioned above, in some embodiments, the memory modules 135 areorganized into groups, e.g., into one group which is memory intensive,another group which is HBM heavy, another group which has limiteddensity and performance, and another group that has a dense capacity.Such groups may have different form factors or be based on differenttechnologies. The controller 137 of the enhanced capability CXL switch130 may route data and commands intelligently based on, for example, aworkload, a tagging, or a quality of service (QoS). For read requests,there may be no routing based on such factors.

The controller 137 of the enhanced capability CXL switch 130 may also(as mentioned above) virtualize the processing-circuit-side addressesand memory-side addresses, making it possible for the controller 137 ofthe enhanced capability CXL switch 130 to determine where data is to bestored. The controller 137 of the enhanced capability CXL switch 130 maymake such a determination based on information or instructions it mayreceive from a processing circuit 115. For example, the operating systemmay provide a memory allocation feature making it possible for anapplication to specify that low-latency storage, or high bandwidthstorage, or persistent storage is to be allocated, and such a request,initiated by the application, may then be taken into account by thecontroller 137 of the enhanced capability CXL switch 130 in determiningwhere (e.g. in which of the memory modules 135) to allocate the memory.For example, storage for which high bandwidth is requested by theapplication may be allocated in memory modules 135 containing HBM,storage for which data persistence is requested by the application maybe allocated in memory modules 135 containing NAND flash, and otherstorage (for which the application has made no requests) may be storedon memory modules 135 containing relatively inexpensive DRAM. In someembodiments, the controller 137 of the enhanced capability CXL switch130 may make determinations about where to store certain data based onnetwork usage patterns. For example, the controller 137 of the enhancedcapability CXL switch 130 may determine, by monitoring usage patterns,that data in a certain range of physical addresses are being accessedmore frequently than other data, and the controller 137 of the enhancedcapability CXL switch 130 may then copy these data into a memory module135 containing HBM, and modify its address translation table so that thedata, in the new location, are stored in the same range of virtualaddresses. In some embodiments one or more of the memory modules 135includes flash memory (e.g., NAND flash), and the controller 137 of theenhanced capability CXL switch 130 implements a flash translation layerfor this flash memory. The flash translation layer may supportoverwriting of processor-side memory locations (by moving the data to adifferent location and marking the previous location of the data asinvalid) and it may perform garbage collection (e.g., erasing a block,after moving, to another block, any valid data in the block, when thefraction of data in the block marked invalid exceeds a threshold).

In some embodiments, the controller 137 of the enhanced capability CXLswitch 130 may facilitate a physical function (PF) to PF transfer. Forexample, if one of the processing circuits 115 needs to move data fromone physical address to another (which may have the same virtualaddresses; this fact need not affect the operation of the processingcircuit 115), or if the processing circuit 115 needs to move databetween two virtual addresses (which the processing circuit 115 wouldneed to have) the controller 137 of the enhanced capability CXL switch130 may supervise the transfer, without the involvement of theprocessing circuit 115. For example, the processing circuit 115 may senda CXL request, and data may be transmitted from one memory module 135 toanother memory module 135 (e.g., the data may be copied from one memorymodule 135 to another memory module 135) behind the enhanced capabilityCXL switch 130 without going to the processing circuit 115. In thissituation, because the processing circuit 115 initiated the CXL request,the processing circuit 115 may need to flush its cache to ensureconsistency. If instead a Type 2 memory device (e.g., one of the memorymodules 135, or an accelerator that may also be connected to the CXLswitch) initiates the CXL request and the switch is not virtualized,then the Type 2 memory device may send a message to the processingcircuit 115 to invalidate the cache.

In some embodiments, the controller 137 of the enhanced capability CXLswitch 130 may facilitate RDMA requests between servers. A remote server105 may initiate such an RDMA request, and the request may be sentthrough the ToR Ethernet switch 110, and arrive at the enhancedcapability CXL switch 130 in the server 105 responding to the RDMArequest (the “local server”). The enhanced capability CXL switch 130 maybe configured to receive such an RDMA request and it may treat a groupof memory modules 135 in the receiving server 105 (i.e., the serverreceiving the RDMA request) as its own memory space. In the localserver, the enhanced capability CXL switch 130 may receive the RDMArequest as a direct RDMA request (i.e., an RDMA request that is notrouted through a processing circuit 115 in the local server) and it maysend a direct response to the RDMA request (i.e., it may send theresponse without it being routed through a processing circuit 115 in thelocal server). In the remote server, the response (e.g., data sent bythe local server) may be received by the enhanced capability CXL switch130 of the remote server, and stored in the memory modules 135 of theremote server, without being routed through a processing circuit 115 inthe remote server.

FIG. 1D shows a system similar to that of FIG. 1C, in which theprocessing circuits 115 are connected to the network interface circuits125 through the enhanced capability CXL switch 130. The enhancedcapability CXL switch 130, the memory modules 135, and the networkinterface circuits 125 are on an expansion socket adapter 140. Theexpansion socket adapter 140 may be a circuit board or module that plugsinto an expansion socket, e.g., a PCIe connector 145, on the motherboardof the server 105. As such, the server may be any suitable server,modified only by the installation of the expansion socket adapter 140 inthe PCIe connector 145. The memory modules 135 may be installed inconnectors (e.g., M.2 connectors) on the expansion socket adapter 140.In such an embodiment, (i) the network interface circuits 125 may beintegrated into the enhanced capability CXL switch 130, or (ii) eachnetwork interface circuit 125 may have a PCIe interface (the networkinterface circuit 125 may be a PCIe endpoint), so that the processingcircuit 115 to which it is connected may communicate with the networkinterface circuit 125 through a root port to endpoint PCIe connection.The controller 137 of the enhanced capability CXL switch 130 (which mayhave a PCIe input port connected to the processing circuit 115 and tothe network interface circuits 125) may communicate with the networkinterface circuit 125 through a peer-to-peer PCIe connection.

According to an embodiment of the present invention, there is provided asystem, including: a first server, including: a stored-programprocessing circuit, a network interface circuit, a cache-coherentswitch, and a first memory module, wherein: the first memory module isconnected to the cache-coherent switch, the cache-coherent switch isconnected to the network interface circuit, and the stored-programprocessing circuit is connected to the cache-coherent switch. In someembodiments, the system further includes a second memory moduleconnected to the cache-coherent switch, wherein the first memory moduleincludes volatile memory and the second memory module includespersistent memory. In some embodiments, the cache-coherent switch isconfigured to virtualize the first memory module and the second memorymodule. In some embodiments, the first memory module includes flashmemory, and the cache-coherent switch is configured to provide a flashtranslation layer for the flash memory. In some embodiments, thecache-coherent switch is configured to: monitor an access frequency of afirst memory location in the first memory module; determine that theaccess frequency exceeds a first threshold; and copy the contents of thefirst memory location into a second memory location, the second memorylocation being in the second memory module. In some embodiments, thesecond memory module includes high bandwidth memory (HBM). In someembodiments, the cache-coherent switch is configured to maintain a tablefor mapping processor-side addresses to memory-side addresses. In someembodiments, the system further includes: a second server, and a networkswitch connected to first server and the second server. In someembodiments, the network switch includes a top of rack (ToR) Ethernetswitch. In some embodiments, the cache-coherent switch is configured toreceive straight remote direct memory access (RDMA) requests, and tosend straight RDMA responses. In some embodiments, the cache-coherentswitch is configured to receive the remote direct memory access (RDMA)requests through the ToR Ethernet switch and through the networkinterface circuit, and to send straight RDMA responses through the ToREthernet switch and through the network interface circuit. In someembodiments, the cache-coherent switch is configured to support aCompute Express Link (CXL) protocol. In some embodiments, the firstserver includes an expansion socket adapter, connected to an expansionsocket of the first server, the expansion socket adapter including: thecache-coherent switch; and a memory module socket, the first memorymodule being connected to the cache-coherent switch through the memorymodule socket. In some embodiments, the memory module socket includes anM.2 socket. In some embodiments, the network interface circuit is on theexpansion socket adapter. According to an embodiment of the presentinvention, there is provided a method for performing remote directmemory access in a computing system, the computing system including: afirst server and a second server, the first server including: astored-program processing circuit, a network interface circuit, acache-coherent switch, and a first memory module, the method including:receiving, by the cache-coherent switch, a straight remote direct memoryaccess (RDMA) request, and sending, by the cache-coherent switch, astraight RDMA response. In some embodiments: the computing systemfurther includes an Ethernet switch, and the receiving of the straightRDMA request includes receiving the straight RDMA request through theEthernet switch. In some embodiments, the method further includes:receiving, by the cache-coherent switch, a read command, from thestored-program processing circuit, for a first memory address,translating, by the cache-coherent switch, the first memory address to asecond memory address, and retrieving, by the cache-coherent switch,data from the first memory module at the second memory address. In someembodiments, the method further includes: receiving data, by thecache-coherent switch, storing, by the cache-coherent switch, the datain the first memory module, and sending, by the cache-coherent switch,to the stored-program processing circuit, a command for invalidating acache line. According to an embodiment of the present invention, thereis provided a system, including: a first server, including: astored-program processing circuit, a network interface circuit,cache-coherent switching means, and a first memory module, wherein: thefirst memory module is connected to the cache-coherent switching means,the cache-coherent switching means is connected to the network interfacecircuit, and the stored-program processing circuit is connected to thecache-coherent switching means.

FIG. 1E shows an embodiment in which each of a plurality of servers 105is connected to a ToR server-linking switch 112, which may be a PCIe 5.0CXL switch, having PCIe capabilities, as illustrated. The server-linkingswitch 112 may include an FPGA or ASIC, and may provide performance (interms of throughput and latency) superior to that of an Ethernet switch.Each of the servers 105 may include a plurality of memory modules 135connected to the server-linking switch 112 through the enhancedcapability CXL switch 130 and through a plurality of PCIe connectors.Each of the servers 105 may also include one or more processing circuits115, and system memory 120, as shown. The server-linking switch 112 mayoperate as a master, and each of the enhanced capability CXL switches130 may operate as a slave, as discussed in further detail below.

In the embodiment of FIG. 1E, the server-linking switch 112 may group orbatch multiple cache requests received from different servers 105, andit may group packets, reducing control overhead. The enhanced capabilityCXL switch 130 may include a slave controller (e.g., a slave FPGA or aslave ASIC) to (i) route data to different memory types based onworkload, (ii) virtualize processor-side addresses to memory-sideaddresses, and (iii) facilitate coherent requests between differentservers 105, bypassing the processing circuits 115. The systemillustrated in FIG. 1E may be CXL 2.0 based, it may include distributedshared memory within a rack, and it may use the ToR server-linkingswitch 112 to natively connect with remote nodes.

The ToR server-linking switch 112 may have an additional networkconnection (e.g., an Ethernet connection, as illustrated, or anotherkind of connection, e.g., a wireless connection such as a WiFiconnection or a 5G connection) for making connections to other serversor to clients. The server-linking switch 112 and the enhanced capabilityCXL switch 130 may each include a controller, which may be or include aprocessing circuit such as an ARM processor. The PCIe interfaces maycomply with the PCIe 5.0 standard or with an earlier version, or with afuture version of the PCIe standard, or interfaces complying with adifferent standard (e.g., NVDIMM-P, CCIX, or OpenCAPI) may be employedinstead of PCIe interfaces. The memory modules 135 may include variousmemory types including DDR4 DRAM, HBM, LDPPR, NAND flash, or solid statedrives (SSDs). The memory modules 135 may be partitioned or containcache controllers to handle multiple memory types, and they may be indifferent form factors, such as HHHL, FHHL, M.2, U.2, mezzanine card,daughter card, E1.S, E1.L, E3.L, or E3.S.

In the embodiment of FIG. 1E, the enhanced capability CXL switch 130 mayenable one-to-many and many-to-one switching, and it may enable a finegrain load-store interface at the flit (64-byte) level. Each server mayhave aggregated memory devices, each device being partitioned intomultiple logical devices each with a respective LD-ID. A ToR switch 112(which may be referred to as a “server-linking switch” enables theone-to-many functionality, and the enhanced capability CXL switch 130 inthe server 105 enables the many-to-one functionality. The server-linkingswitch 112 may be a PCIe switch, or a CXL switch, or both. In such asystem, the requesters may be the processing circuits 115 of themultiple servers 105, the responders may be the many aggregated memorymodules 135. The hierarchy of two switches (with the master switchbeing, as mentioned above, the server-linking switch 112, and the slaveswitch being the enhanced capability CXL switch 130) enables any-anycommunication. Each of the memory modules 135 may have one physicalfunction (PF) and as many as 16 isolated logical devices. In someembodiments the number of logical devices (e.g., the number ofpartitions) may be limited (e.g. to 16), and one control partition(which may be a physical function used for controlling the device) mayalso be present. Each of the memory modules 135 may be a Type 2 devicewith cxl.cache, cxl.mem and cxl.io and address translation service (ATS)implementation to deal with cache line copies that the processingcircuits 115 may hold. The enhanced capability CXL switch 130 and afabric manager may control discovery of the memory modules 135 and (i)perform device discovery, and virtual CXL software creation, and (ii)bind virtual to physical ports. As in the embodiments of FIGS. 1A-1D,the fabric manager may operate through connections over an SMBussideband. An interface to the memory modules 135, which may beIntelligent Platform Management Interface (IPMI) or an interface thatcomplies with the Redfish standard (and that may also provide additionalfeatures not required by the standard), may enable configurability.

As mentioned above, some embodiments implement a hierarchical structurewith a master controller (which may be implemented in an FPGA or in anASIC) being part of the server-linking switch 112, and a slavecontroller being part of the enhanced capability CXL switch 130, toprovide a load-store interface (i.e., an interface having cache-line(e.g., 64 byte) granularity and that operates within the coherencedomain without software driver involvement). Such a load-store interfacemay extend the coherence domain beyond an individual server, or CPU orhost, and may involve a physical medium that is either electrical oroptical (e.g., an optical connection with electrical-to-opticaltransceivers at both ends). In operation, the master controller (in theserver-linking switch 112) boots (or “reboots”) and configures all theservers 105 on the rack. The master controller may have visibility onall the hosts, and it may (i) discover each server and discover how manyservers 105 and memory modules 135 exist in the server cluster, (ii)configure each of the servers 105 independently, (iii) enable or disablesome blocks of memory (e.g., enable or disable any of the memory modules135) on different servers, based on, e.g., the configuration of theracks, (iv) control access (e.g., which server can control which otherserver), (v) implement flow control (e.g. it may, since all host anddevice requests go through the master, transmit data from the one serverto another server, and perform flow control on the data), (vi) group orbatch requests or packets (e.g., multiple cache requests being receivedby the master from different servers 105), and (vii) receive remotesoftware updates, broadcast communications, and the like. In batch mode,the server-linking switch 112 may receive a plurality of packetsdestined for the same server (e.g., destined for a first server) andsend them together (i.e., without a pause between them) to the firstserver. For example, server-linking switch 112 may receive a firstpacket, from a second server, and a second packet, from a third server,and transmit the first packet and the second packet, together, to thefirst server. Each of the servers 105 may expose, to the mastercontroller, (i) an IPMI network interface, (ii) a system event log(SEL), and (iii) a board management controller (BMC), enabling themaster controller to measure performance, to measure reliability on thefly, and to reconfigure the servers 105.

In some embodiments, a software architecture that facilitates a highavailability load-store interface is used. Such a software architecturemay provide reliability, replication, consistency, system coherence,hashing, caching, and persistence. The software architecture may providereliability (in a system with a large number of servers), by performingperiodic hardware checks of the CXL device components via IPMI. Forexample, the server-linking switch 112 may query a status of a memoryserver 150, through an IPMI interface, of the memory server 150,querying, for example, the power status (whether the power supplies ofthe memory server 150 are operating properly), the network status(whether the interface to the server-linking switch 112 is operatingproperly) and an error check status (whether an error condition ispresent in any of the subsystems of the memory server 150). The softwarearchitecture may provide replication, in that the master controller mayreplicate data stored in the memory modules 135 and maintain dataconsistency across replicas.

The software architecture may provide consistency in that the mastercontroller may be configured with different consistency levels, and theserver-linking switch 112 may adjust the packet format according to theconsistency level to be maintained. For example, if eventual consistencyis being maintained, the server-linking switch 112 may reorder therequests, while to maintain strict consistency, the server-linkingswitch 112 may maintain a scoreboard of all requests with precisetimestamps at the switches. The software architecture may provide systemcoherence in that multiple processing circuits 115 may be reading fromor writing to the same memory address, and the master controller may, tomaintain coherence, be responsible for reaching the home node of theaddress (using a directory lookup) or broadcasting the request on acommon bus.

The software architecture may provide hashing in that the server-linkingswitch 112 and the enhanced capability CXL switch may maintain a virtualmapping of addresses which may use consistent hashing with multiple hashfunctions to evenly map data to all CXL devices across all nodes atboot-up (or to adjust when one server goes down or comes up). Thesoftware architecture may provide caching in that the master controllermay designate certain memory partitions (e.g., in a memory module 135that includes HBM or a technology with similar capabilities) to act ascache (employing write-through caching or write-back caching, forexample). The software architecture may provide persistence in that themaster controller and the slave controller may manage persistent domainsand flushes.

In some embodiments, the capabilities of the CXL switch are integratedinto the controller of a memory module 135. In such an embodiment, theserver-linking switch 112 may nonetheless act as a master and haveenhanced features as discussed elsewhere herein. The server-linkingswitch 112 may also manage other storage devices in the system, and itmay have an Ethernet connection (e.g., a 100 GbE connection), forconnecting, e.g., to client machines that are not part of the PCIenetwork formed by the server-linking switch 112.

In some embodiments, the server-linking switch 112 has enhancedcapabilities and also includes an integrated CXL controller. In otherembodiments, the server-linking switch 112 is only a physical routingdevice, and each server 105 includes a master CXL controller. In such anembodiment, masters across different servers may negotiate amaster-slave architecture. The intelligence functions of (i) theenhanced capability CXL switch 130 and of (ii) the server-linking switch112 may be implemented in one or more FPGAs, one or more ASICs, one ormore ARM processors, or in one or more SSD devices with computecapabilities. The server-linking switch 112 may perform flow control,e.g., by reordering independent requests. In some embodiments, becausethe interface is load-store, RDMA is optional but there may beintervening RDMA requests that use the PCIe physical medium (instead of100 GbE). In such an embodiment, a remote host may initiate an RDMArequest, which may be transmitted to the enhanced capability CXL switch130 through the server-linking switch 112. The server-linking switch 112and the enhanced capability CXL switch 130 may prioritize RDMA 4 KBrequests, or CXL's flit (64-byte) requests.

As in the embodiment of FIGS. 1C and 1D, the enhanced capability CXLswitch 130 may be configured to receive such an RDMA request and it maytreat a group of memory modules 135 in the receiving server 105 (i.e.,the server receiving the RDMA request) as its own memory space. Further,the enhanced capability CXL switch 130 may virtualize across theprocessing circuits 115 and initiate RDMA request on remote enhancedcapability CXL switches 130 to move data back and forth between servers105, without the processing circuits 115 being involved.

FIG. 1F shows a system similar to that of FIG. 1E, in which theprocessing circuits 115 are connected to the network interface circuits125 through the enhanced capability CXL switch 130. As in the embodimentof FIG. 1D, in FIG. 1F the enhanced capability CXL switch 130, thememory modules 135, and the network interface circuits 125 are on anexpansion socket adapter 140. The expansion socket adapter 140 may be acircuit board or module that plugs into an expansion socket, e.g., aPCIe connector 145, on the motherboard of the server 105. As such, theserver may be any suitable server, modified only by the installation ofthe expansion socket adapter 140 in the PCIe connector 145. The memorymodules 135 may be installed in connectors (e.g., M.2 connectors) on theexpansion socket adapter 140. In such an embodiment, (i) the networkinterface circuits 125 may be integrated into the enhanced capabilityCXL switch 130, or (ii) each network interface circuit 125 may have aPCIe interface (the network interface circuit 125 may be a PCIeendpoint), so that the processing circuit 115 to which it is connectedmay communicate with the network interface circuit 125 through a rootport to endpoint PCIe connection, and the controller 137 of the enhancedcapability CXL switch 130 (which may have a PCIe input port connected tothe processing circuit 115 and to the network interface circuits 125)may communicate with the network interface circuit 125 through apeer-to-peer PCIe connection.

According to an embodiment of the present invention, there is provided asystem, including: a first server, including: a stored-programprocessing circuit, a cache-coherent switch, and a first memory module;and a second server; and a server-linking switch connected to the firstserver and to the second server, wherein: the first memory module isconnected to the cache-coherent switch, the cache-coherent switch isconnected to the server-linking switch, and the stored-programprocessing circuit is connected to the cache-coherent switch. In someembodiments, the server-linking switch includes a Peripheral ComponentInterconnect Express (PCIe) switch. In some embodiments, theserver-linking switch includes a Compute Express Link (CXL) switch. Insome embodiments, the server-linking switch includes a top of rack (ToR)CXL switch. In some embodiments, the server-linking switch is configuredto discover the first server. In some embodiments, the server-linkingswitch is configured to cause the first server to reboot. In someembodiments, the server-linking switch is configured to cause thecache-coherent switch to disable the first memory module. In someembodiments, the server-linking switch is configured to transmit datafrom the second server to the first server, and to perform flow controlon the data. In some embodiments, the system further includes a thirdserver connected to the server-linking switch, wherein: theserver-linking switch is configured to: receive a first packet, from thesecond server, receive a second packet, from the third server, andtransmit the first packet and the second packet to the first server. Insome embodiments, the system further includes a second memory moduleconnected to the cache-coherent switch, wherein the first memory moduleincludes volatile memory and the second memory module includespersistent memory. In some embodiments, the cache-coherent switch isconfigured to virtualize the first memory module and the second memorymodule. In some embodiments, the first memory module includes flashmemory, and the cache-coherent switch is configured to provide a flashtranslation layer for the flash memory. In some embodiments, the firstserver includes an expansion socket adapter, connected to an expansionsocket of the first server, the expansion socket adapter including: thecache-coherent switch; and a memory module socket, the first memorymodule being connected to the cache-coherent switch through the memorymodule socket. In some embodiments, the memory module socket includes anM.2 socket. In some embodiments: the cache-coherent switch is connectedto the server-linking switch through a connector, and the connector ison the expansion socket adapter. According to an embodiment of thepresent invention, there is provided a method for performing remotedirect memory access in a computing system, the computing systemincluding: a first server, a second server, a third server, and aserver-linking switch connected to the first server, to the secondserver, and to the third server, the first server including: astored-program processing circuit, a cache-coherent switch, and a firstmemory module, the method including: receiving, by the server-linkingswitch, a first packet, from the second server, receiving, by theserver-linking switch, a second packet, from the third server, andtransmitting the first packet and the second packet to the first server.In some embodiments, the method further includes: receiving, by thecache-coherent switch, a straight remote direct memory access (RDMA)request, and sending, by the cache-coherent switch, a straight RDMAresponse. In some embodiments, the receiving of the straight RDMArequest includes receiving the straight RDMA request through theserver-linking switch. In some embodiments, the method further includes:receiving, by the cache-coherent switch, a read command, from thestored-program processing circuit, for a first memory address,translating, by the cache-coherent switch, the first memory address to asecond memory address, and retrieving, by the cache-coherent switch,data from the first memory module at the second memory address.According to an embodiment of the present invention, there is provided asystem, including: a first server, including: a stored-programprocessing circuit, cache-coherent switching means, a first memorymodule; and a second server; and a server-linking switch connected tothe first server and to the second server, wherein: the first memorymodule is connected to the cache-coherent switching means, thecache-coherent switching means is connected to the server-linkingswitch, and the stored-program processing circuit is connected to thecache-coherent switching means.

FIG. 1G shows an embodiment in which each of a plurality of memoryservers 150 is connected to a ToR server-linking switch 112, which maybe a PCIe 5.0 CXL switch, as illustrated. As in the embodiment of FIGS.1E and 1F, the server-linking switch 112 may include an FPGA or ASIC,and may provide performance (in terms of throughput and latency)superior to that of an Ethernet switch. As in the embodiment of FIGS. 1Eand 1F, the memory server 150 may include a plurality of memory modules135 connected to the server-linking switch 112 through a plurality ofPCIe connectors. In the embodiment of FIG. 1G, the processing circuits115 and system memory 120 may be absent, and the primary purpose of thememory server 150 may be to provide memory, for use by other servers 105having computing resources.

In the embodiment of FIG. 1G, the server-linking switch 112 may group orbatch multiple cache requests received from different memory servers150, and it may group packets, reducing control overhead. The enhancedcapability CXL switch 130 may include composable hardware buildingblocks to (i) route data to different memory types based on workload,and (ii) virtualize processor-side addresses (translating such addressesto memory-side addresses). The system illustrated in FIG. 1G may be CXL2.0 based, it may include composable and disaggregated shared memorywithin a rack, and it may use the ToR server-linking switch 112 toprovide pooled (i.e., aggregated) memory to remote devices.

The ToR server-linking switch 112 may have an additional networkconnection (e.g., an Ethernet connection, as illustrated, or anotherkind of connection, e.g., a wireless connection such as a WiFiconnection or a 5G connection) for making connections to other serversor to clients. The server-linking switch 112 and the enhanced capabilityCXL switch 130 may each include a controller, which may be or include aprocessing circuit such as an ARM processor. The PCIe interfaces maycomply with the PCIe 5.0 standard or with an earlier version, or with afuture version of the PCIe standard, or a different standard (e.g.,NVDIMM-P, CCIX, or OpenCAPI) may be employed instead of PCIe. The memorymodules 135 may include various memory types including DDR4 DRAM, HBM,LDPPR, NAND flash, and solid state drives (SSDs). The memory modules 135may be partitioned or contain cache controllers to handle multiplememory types, and they may be in different form factors, such as HHHL,FHHL, M.2, U.2, mezzanine card, daughter card, E1.S, E1.L, E3.L, orE3.S.

In the embodiment of FIG. 1G, the enhanced capability CXL switch 130 mayenable one-to-many and many-to-one switching, and it may enable a finegrain load-store interface at the flit (64-byte) level. Each memoryserver 150 may have aggregated memory devices, each device beingpartitioned into multiple logical devices each with a respective LD-ID.The enhanced capability CXL switch 130 may include a controller 137(e.g., an ASIC or an FPGA), and a circuit (which may be separate from,or part of, such an ASIC or FPGA) for device discovery, enumeration,partitioning, and presenting physical address ranges. Each of the memorymodules 135 may have one physical function (PF) and as many as 16isolated logical devices. In some embodiments the number of logicaldevices (e.g., the number of partitions) may be limited (e.g. to 16),and one control partition (which may be a physical function used forcontrolling the device) may also be present. Each of the memory modules135 may be a Type 2 device with cxl.cache, cxl.mem and cxl.io andaddress translation service (ATS) implementation to deal with cache linecopies that the processing circuits 115 may hold.

The enhanced capability CXL switch 130 and a fabric manager may controldiscovery of the memory modules 135 and (i) perform device discovery,and virtual CXL software creation, and (ii) bind virtual to physicalports. As in the embodiments of FIGS. 1A-1D, the fabric manager mayoperate through connections over an SMBus sideband. An interface to thememory modules 135, which may be Intelligent Platform ManagementInterface (IPMI) or an interface that complies with the Redfish standard(and that may also provide additional features not required by thestandard), may enable configurability.

Building blocks, for the embodiment of FIG. 1G, may include (asmentioned above) a CXL controller 137 implemented on an FPGA or on anASIC, switching to enable aggregating of memory devices (e.g., of thememory modules 135), SSDs, accelerators (GPUs, NICs), CXL and PCIe5connectors, and firmware to expose device details to the advancedconfiguration and power interface (ACPI) tables of the operating system,such as the heterogeneous memory attribute table (HMAT) or the staticresource affinity table SRAT.

In some embodiments, the system provides composability. The system mayprovide an ability to online and offline CXL devices and otheraccelerators based on the software configuration, and it may be capableof grouping accelerator, memory, storage device resources and rationingthem to each memory server 150 in the rack. The system may hide thephysical address space and provide transparent cache using fasterdevices like HBM and SRAM.

In the embodiment of FIG. 1G, the controller 137 of the enhancedcapability CXL switch 130 may (i) manage the memory modules 135, (ii)integrate and control heterogeneous devices such as NICs, SSDs, GPUs,DRAM, and (iii) effect dynamic reconfiguration of storage to memorydevices by power-gating. For example, the ToR server-linking switch 112may disable power (i.e., shut off power, or reduce power) to one of thememory modules 135 (by instructing the enhanced capability CXL switch130 to disable power to the memory module 135). The enhanced capabilityCXL switch 130 may then disable power to the memory module 135, uponbeing instructed, by the server-linking switch 112, to disable power tothe memory module. Such disabling may conserve power, and it may improvethe performance (e.g., the throughput and latency) of other memorymodules 135 in the memory server 150. Each remote server 105 may see adifferent logical view of memory modules 135 and their connections basedon negotiation. The controller 137 of the enhanced capability CXL switch130 may maintain state so that each remote server maintains allottedresources and connections, and it may perform compression ordeduplication of memory to save memory capacity (using a configurablechunk size). The disaggregated rack of FIG. 1G may have its own BMC. Italso may expose an IPMI network interface and a system event log (SEL)to remote devices, enabling the master (e.g., a remote server usingstorage provided by the memory servers 150) to measure performance andreliability on the fly, and to reconfigure the disaggregated rack. Thedisaggregated rack of FIG. 1G may provide reliability, replication,consistency, system coherence, hashing, caching, and persistence, in amanner analogous to that described herein for the embodiment of FIG. 1E,with, e.g., coherence being provided with multiple remote serversreading from or writing to the same memory address, and with each remoteserver being configured with different consistency levels. In someembodiments, the server-linking switch maintains eventual consistencybetween data stored on a first memory server, and data stored on asecond memory server. The server-linking switch 112 may maintaindifferent consistency levels for different pairs of servers; forexample, the server-linking switch may also maintain, between datastored on the first memory server, and data stored on a third memoryserver, a consistency level that is strict consistency, sequentialconsistency, causal consistency, or processor consistency. The systemmay employ communications in “local-band” (the server-linking switch112) and “global-band” (disaggregated server) domains. Writes may beflushed to the “global band” to be visible to new reads from otherservers. The controller 137 of the enhanced capability CXL switch 130may manage persistent domains and flushes separately for each remoteserver. For example, the cache-coherent switch may monitor a fullness ofa first region of memory (volatile memory, operating as a cache), and,when the fullness level exceeds a threshold, the cache-coherent switchmay move data from the first region of memory to a second region ofmemory, the second region of memory being in persistent memory. Flowcontrol may be handled in that priorities may be established, by thecontroller 137 of the enhanced capability CXL switch 130, among remoteservers, to present different perceived latencies and bandwidths.

According to an embodiment of the present invention, there is provided asystem, including: a first memory server, including: a cache-coherentswitch, and a first memory module; and a second memory server; and aserver-linking switch connected to the first memory server and to thesecond memory server, wherein: the first memory module is connected tothe cache-coherent switch, and the cache-coherent switch is connected tothe server-linking switch. In some embodiments, the server-linkingswitch is configured to disable power to the first memory module. Insome embodiments: the server-linking switch is configured to disablepower to the first memory module by instructing the cache-coherentswitch to disable power to the first memory module, and thecache-coherent switch is configured to disable power to the first memorymodule, upon being instructed, by the server-linking switch, to disablepower to the first memory module. In some embodiments, thecache-coherent switch is configured to perform deduplication within thefirst memory module. In some embodiments, the cache-coherent switch isconfigured to compress data and to store compressed data in the firstmemory module. In some embodiments, the server-linking switch isconfigured to query a status of the first memory server. In someembodiments, the server-linking switch is configured to query a statusof the first memory server through an Intelligent Platform ManagementInterface (IPMI). In some embodiments, the querying of a status includesquerying a status selected from the group consisting of a power status,a network status, and an error check status. In some embodiments, theserver-linking switch is configured to batch cache requests directed tothe first memory server. In some embodiments, the system furtherincludes a third memory server connected to the server-linking switch,wherein the server-linking switch is configured to maintain, betweendata stored on the first memory server and data stored on the thirdmemory server, a consistency level selected from the group consisting ofstrict consistency, sequential consistency, causal consistency, andprocessor consistency. In some embodiments, the cache-coherent switch isconfigured to: monitor a fullness of a first region of memory, and movedata from the first region of memory to a second region of memory,wherein: the first region of memory is in volatile memory, and thesecond region of memory is in persistent memory. In some embodiments,the server-linking switch includes a Peripheral Component InterconnectExpress (PCIe) switch. In some embodiments, the server-linking switchincludes a Compute Express Link (CXL) switch. In some embodiments, theserver-linking switch includes a top of rack (ToR) CXL switch. In someembodiments, the server-linking switch is configured to transmit datafrom the second memory server to the first memory server, and to performflow control on the data. In some embodiments, the system furtherincludes a third memory server connected to the server-linking switch,wherein: the server-linking switch is configured to: receive a firstpacket, from the second memory server, receive a second packet, from thethird memory server, and transmit the first packet and the second packetto the first memory server. According to an embodiment of the presentinvention, there is provided a method for performing remote directmemory access in a computing system, the computing system including: afirst memory server; a first server; a second server; and aserver-linking switch connected to the first memory server, to the firstserver, and to the second server, the first memory server including: acache-coherent switch, and a first memory module; the first serverincluding: a stored-program processing circuit; the second serverincluding: a stored-program processing circuit; the method including:receiving, by the server-linking switch, a first packet, from the firstserver; receiving, by the server-linking switch, a second packet, fromthe second server; and transmitting the first packet and the secondpacket to the first memory server. In some embodiments, the methodfurther includes: compressing data, by the cache-coherent switch, andstoring the data in the first memory module. In some embodiments, themethod further includes: querying, by the server-linking switch, astatus of the first memory server. According to an embodiment of thepresent invention, there is provided a system, including: a first memoryserver, including: a cache-coherent switch, and a first memory module;and a second memory server; and server-linking switching means connectedto the first memory server and to the second memory server, wherein: thefirst memory module is connected to the cache-coherent switch, and thecache-coherent switch is connected to the server-linking switchingmeans.

FIGS. 2A-2D are flow charts for various embodiments. In the embodimentsof these flow charts, the processing circuits 115 are CPUs; in otherembodiments they may be other processing circuits (e.g., GPUs).Referring to FIG. 2A, the controller 137 of a memory module 135 of theembodiment of FIGS. 1A and 1B, or the enhanced capability CXL switch 130of any of the embodiments of FIGS. 1C-1G may virtualize across theprocessing circuit 115 and initiate an RDMA request on an enhancedcapability CXL switch 130 in another server 105, to move data back andforth between servers 105, without involving a processing circuit 115 ineither server (with the virtualization being handled by the controller137 of the enhanced capability CXL switches 130). For example, at 205,the controller 137 of the memory module 135, or the enhanced capabilityCXL switch 130, generates an RDMA request for additional remote memory(e.g., CXL memory or aggregated memory); at 210, the network interfacecircuits 125 transmit the request to the ToR Ethernet switch 110 (whichmay have an RDMA interface), bypassing processing circuits; at 215, theToR Ethernet switch 110 routes the RDMA request to the remote the server105 for processing by the controller 137 of a memory module 135, or by aremote enhanced capability CXL switch 130, via RDMA access to remoteaggregated memory, bypassing the remote processing circuit 115; at 220,the ToR Ethernet switch 110 receives the processed data and routes thedata to the local memory module 135, or to the local enhanced capabilityCXL switch 130, bypassing the local processing circuits 115 via RDMA;and, at 222, the controller 137 of a memory module 135 of the embodimentof FIGS. 1A and 1B, or the enhanced capability CXL switch 130 receivesthe RDMA response straightly (e.g., without it being forwarded by theprocessing circuits 115).

In such an embodiment, the controller 137 of the remote memory module135, or the enhanced capability CXL switch 130 of the remote the server105, is configured to receive straight remote direct memory access(RDMA) requests and to send straight RDMA responses. As used herein, thecontroller 137 of the remote memory module 135 receiving, or theenhanced capability CXL switch 130 receiving, “straight RDMA requests”(or receiving such requests “straightly”) means receiving, by thecontroller 137 of the remote memory module 135, or by the enhancedcapability CXL switch 130, such requests without their being forwardedor otherwise processed by a processing circuit 115 of the remote server,and sending, by the controller 137 of the remote memory module 135, orby the enhanced capability CXL switch 130, “straight RDMA responses” (orsending such requests “straightly”) means sending such responses withouttheir being forwarded or otherwise processed by a processing circuit 115of the remote server.

Referring to FIG. 2B, in another embodiment, RDMA may be performed withthe processing circuit of the remote server being involved in thehandling of the data. For example, at 225, a processing circuit 115 maytransmit data or a workload request over Ethernet; at 230, the ToREthernet switch 110 may receive the request and route it to thecorresponding server 105 of the plurality of servers 105; at 235, therequest may be received, within the server, over port(s) of the networkinterface circuits 125 (e.g., 100 GbE-enabled NIC); at 240, theprocessing circuits 115 (e.g., x86 processing circuits) may receive therequest from the network interface circuits 125; and, at 245, theprocessing circuits 115 may process the request (e.g., together), usingDDR and additional memory resources via the CXL 2.0 protocol to sharethe memory (which, in the embodiment of FIGS. 1A and 1B, may beaggregated memory).

Referring to FIG. 2C, in the embodiment of FIG. 1E, RDMA may beperformed with the processing circuit of the remote server beinginvolved in the handling of the data. For example, at 225, a processingcircuit 115 may transmit data or a workload request over Ethernet orPCie at 230, the ToR Ethernet switch 110 may receive the request androute it to the corresponding server 105 of the plurality of servers105; at 235, the request may be received, within the server, overport(s) of the PCIe connector; at 240, the processing circuits 115(e.g., x86 processing circuits) may receive the request from the networkinterface circuits 125; and, at 245, the processing circuits 115 mayprocess the request (e.g., together), using DDR and additional memoryresources via the CXL 2.0 protocol to share the memory (which, in theembodiment of FIGS. 1A and 1B, may be aggregated memory). At 250, theprocessing circuit 115 may identify a requirement to access memorycontents (e.g., DDR or aggregated memory contents) from a differentserver; at 252 the processing circuit 115 may send the request for saidmemory contents (e.g., DDR or aggregated memory contents) from adifferent server, via a CXL protocol (e.g., CXL 1.1 or CXL 2.0); at 254,the request propagates through the local PCIe connector to theserver-linking switch 112, which then transmits the request to a secondPCIe connector of a second server on the rack; at 256, the secondprocessing circuits 115 (e.g., x86 processing circuits) receive therequest from the second PCIe connector; at 258, the second processingcircuits 115 may process the request (e.g., retrieval of memorycontents) together, using second DDR and second additional memoryresources via the CXL 2.0 protocol to share the aggregated memory; and,at 260, the second processing circuits (e.g., x86 processing circuits)transmit the result of the request back to the original processingcircuits via respective PCIe connectors and through the server-linkingswitch 112.

Referring to FIG. 2D, in the embodiment of FIG. 1G, RDMA may beperformed with the processing circuit of the remote server beinginvolved in the handling of the data. For example; at 225, a processingcircuit 115 may transmit data or a workload request over Ethernet; at230, the ToR Ethernet switch 110 may receive the request and route it tothe corresponding server 105 of the plurality of servers 105; at 235,the request may be received, within the server, over port(s) of thenetwork interface circuits 125 (e.g., 100 GbE-enabled NICs). At 262, amemory module 135 receives the request from the PCIe connector; at 264,the controller of the memory module 135 processes the request, usinglocal memory; at 250, the controller of the memory module 135 identifiesa requirement to access memory contents (e.g., aggregated memorycontents) from a different server; at 252, the controller of the memorymodule 135 sends request for said memory contents (e.g., aggregatedmemory contents) from a different server via the CXL protocol; at 254the request propagates through the local PCIe connector to theserver-linking switch 112, which then transmits the request to a secondPCIe connector of a second server on the rack; and at 266, the secondPCIe connector provides access via the CXL protocol to share theaggregated memory to allow the controller of the memory module 135 toretrieve memory contents.

As used herein, a “server” is a computing system including at least onestored-program processing circuit (e.g., a processing circuit 115), atleast one memory resource (e.g., a system memory 120), and at least onecircuit for providing network connectivity (e.g., a network interfacecircuit 125). As used herein, “a portion of” something means “at leastsome of” the thing, and as such may mean less than all of, or all of,the thing. As such, “a portion of” a thing includes the entire thing asa special case, i.e., the entire thing is an example of a portion of thething.

The background provided in the Background section of the presentdisclosure section is included only to set context, and the content ofthis section is not admitted to be prior art. Any of the components orany combination of the components described (e.g., in any systemdiagrams included herein) may be used to perform one or more of theoperations of any flow chart included herein. Further, (i) theoperations are example operations, and may involve various additionalsteps not explicitly covered, and (ii) the temporal order of theoperations may be varied.

The term “processing circuit” or “controller means” is used herein tomean any combination of hardware, firmware, and software, employed toprocess data or digital signals. Processing circuit hardware mayinclude, for example, application specific integrated circuits (ASICs),general purpose or special purpose central processing units (CPUs),digital signal processors (DSPs), graphics processing units (GPUs), andprogrammable logic devices such as field programmable gate arrays(FPGAs). In a processing circuit, as used herein, each function isperformed either by hardware configured, i.e., hard-wired, to performthat function, or by more general purpose hardware, such as a CPU,configured to execute instructions stored in a non-transitory storagemedium. A processing circuit may be fabricated on a single printedcircuit board (PCB) or distributed over several interconnected PCBs. Aprocessing circuit may contain other processing circuits; for example aprocessing circuit may include two processing circuits, an FPGA and aCPU, interconnected on a PCB.

As used herein, a “controller” includes a circuit, and a controller mayalso be referred to as a “control circuit” or a “controller circuit”.Similarly, a “memory module” may also be referred to as a “memory modulecircuit” or as a “memory circuit”. As used herein, the term “array”refers to an ordered set of numbers regardless of how stored (e.g.,whether stored in consecutive memory locations, or in a linked list). Asused herein, when a second number is “within Y %” of a first number, itmeans that the second number is at least (1−Y/100) times the firstnumber and the second number is at most (1+Y/100) times the firstnumber. As used herein, the term “or” should be interpreted as “and/or”,such that, for example, “A or B” means any one of “A” or “B” or “A andB”.

As used herein, when a method (e.g., an adjustment) or a first quantity(e.g., a first variable) is referred to as being “based on” a secondquantity (e.g., a second variable) it means that the second quantity isan input to the method or influences the first quantity, e.g., thesecond quantity may be an input (e.g., the only input, or one of severalinputs) to a function that calculates the first quantity, or the firstquantity may be equal to the second quantity, or the first quantity maybe the same as (e.g., stored at the same location or locations inmemory) as the second quantity.

It will be understood that, although the terms “first”, “second”,“third”, etc., may be used herein to describe various elements,components, regions, layers and/or sections, these elements, components,regions, layers and/or sections should not be limited by these terms.These terms are only used to distinguish one element, component, region,layer or section from another element, component, region, layer orsection. Thus, a first element, component, region, layer or sectiondiscussed herein could be termed a second element, component, region,layer or section, without departing from the spirit and scope of theinventive concept.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”,“above”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that such spatially relative terms are intended to encompassdifferent orientations of the device in use or in operation, in additionto the orientation depicted in the figures. For example, if the devicein the figures is turned over, elements described as “below” or“beneath” or “under” other elements or features would then be oriented“above” the other elements or features. Thus, the example terms “below”and “under” can encompass both an orientation of above and below. Thedevice may be otherwise oriented (e.g., rotated 90 degrees or at otherorientations) and the spatially relative descriptors used herein shouldbe interpreted accordingly. In addition, it will also be understood thatwhen a layer is referred to as being “between” two layers, it can be theonly layer between the two layers, or one or more intervening layers mayalso be present.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcept. As used herein, the terms “substantially,” “about,” and similarterms are used as terms of approximation and not as terms of degree, andare intended to account for the inherent deviations in measured orcalculated values that would be recognized by those of ordinary skill inthe art. As used herein, the singular forms “a” and “an” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising”, when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof. As used herein, the term “and/or”includes any and all combinations of one or more of the associatedlisted items. Expressions such as “at least one of,” when preceding alist of elements, modify the entire list of elements and do not modifythe individual elements of the list. Further, the use of “may” whendescribing embodiments of the inventive concept refers to “one or moreembodiments of the present disclosure”. Also, the term “exemplary” isintended to refer to an example or illustration. As used herein, theterms “use,” “using,” and “used” may be considered synonymous with theterms “utilize,” “utilizing,” and “utilized,” respectively.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to”, “coupled to”, or “adjacent to” anotherelement or layer, it may be directly on, connected to, coupled to, oradjacent to the other element or layer, or one or more interveningelements or layers may be present. In contrast, when an element or layeris referred to as being “directly on”, “directly connected to”,“directly coupled to”, or “immediately adjacent to” another element orlayer, there are no intervening elements or layers present.

Any numerical range recited herein is intended to include all sub-rangesof the same numerical precision subsumed within the recited range. Forexample, a range of “1.0 to 10.0” or “between 1.0 and 10.0” is intendedto include all subranges between (and including) the recited minimumvalue of 1.0 and the recited maximum value of 10.0, that is, having aminimum value equal to or greater than 1.0 and a maximum value equal toor less than 10.0, such as, for example, 2.4 to 7.6. Any maximumnumerical limitation recited herein is intended to include all lowernumerical limitations subsumed therein and any minimum numericallimitation recited in this specification is intended to include allhigher numerical limitations subsumed therein.

Although exemplary embodiments of system and method for managing memoryresources have been specifically described and illustrated herein, manymodifications and variations will be apparent to those skilled in theart. Accordingly, it is to be understood that system and method formanaging memory resources constructed according to principles of thisdisclosure may be embodied other than as specifically described herein.The invention is also defined in the following claims, and equivalentsthereof.

What is claimed is:
 1. A system, comprising: a first server, comprising:a processing circuit, a first switch configured to adhere to a cachecoherent protocol, and a first memory device; and a second switchconnected to the first server, wherein: the first memory device isconnected to the first switch via a first interface, the first switch isconnected to the second switch, and the processing circuit is connectedto the first switch via a second interface different from the firstinterface.
 2. The system of claim 1, wherein the second switch comprisesa Peripheral Component Interconnect Express (PCIe) switch.
 3. The systemof claim 1, wherein the second switch comprises a Compute Express Link(CXL) switch.
 4. The system of claim 3, wherein the second switchcomprises a top of rack (ToR) CXL switch.
 5. The system of claim 1,wherein the second switch is configured to discover the first server. 6.The system of claim 1, wherein the second switch is configured to causethe first server to reboot.
 7. The system of claim 1, wherein the secondswitch is configured to cause the first switch to disable the firstmemory device.
 8. The system of claim 1, wherein the second switch isconfigured to transmit data from a second server to the first server,and to perform flow control on the data.
 9. The system of claim 1,further comprising a second server and a third server connected to thesecond switch, wherein: the second switch is configured to: receive afirst packet, from the second server, receive a second packet, from thethird server, and transmit the first packet and the second packet to thefirst server.
 10. The system of claim 1, further comprising a secondmemory device connected to the first switch, wherein the first memorydevice comprises volatile memory and the second memory device comprisespersistent memory.
 11. The system of claim 10, wherein the first switchis configured to virtualize the first memory device and the secondmemory device.
 12. The system of claim 11, wherein the first memorydevice comprises flash memory, and the first switch is configured toprovide a flash translation layer for the flash memory.
 13. The systemof claim 1, wherein the first server comprises an expansion socketadapter, connected to an expansion socket of the first server, theexpansion socket adapter comprising: the first switch; and a memorymodule socket, the first memory device being connected to the firstswitch through the memory module socket.
 14. The system of claim 13,wherein the memory module socket comprises an M.2 socket.
 15. The systemof claim 13, wherein: the first switch is connected to the second switchthrough a connector, and the connector is on the expansion socketadapter.
 16. A method for performing remote direct memory access in acomputing system, the computing system comprising: a first server; asecond server; and a second switch connected to the first server and tothe second server, the first server comprising: a processing circuit, afirst switch configured to adhere to a cache coherent protocol, and amemory device, wherein the memory device is connected to the firstswitch via a first interface, and the processing circuit is connected tothe first switch via a second interface different from the firstinterface, wherein the second switch is configured to: receive a packetfrom the second server; and transmit the packet to the first server. 17.The method of claim 16, further comprising: receiving, by the firstswitch, a remote direct memory access (RDMA) request; and sending, bythe first switch, a RDMA response.
 18. The method of claim 17, whereinthe receiving of the RDMA request comprises receiving the RDMA requestthrough the second switch.
 19. The method of claim 17, furthercomprising: receiving, by the first switch, a read command, from theprocessing circuit, for a first memory address; translating, by thefirst switch, the first memory address to a second memory address; andretrieving, by the first switch, data from the memory device at thesecond memory address.
 20. A system, comprising: a server, comprising: aprocessing circuit, first switching means, a memory device; and a secondswitch connected to the server, wherein: the memory device is connectedto the first switching means via a first interface, the first switchingmeans is connected to the second switch, and the processing circuit isconnected to the first switching means via a second interface differentfrom the first interface.